Tektronix Introduces Logic Protocol Analyzer Test Solution for PCI Express 3.0

04/15/2010

Tektronix, Inc., a leading worldwide provider of test, measurement and monitoring instrumentation, announced a comprehensive test solution for PCI Express 3.0, the next generation PCIe specification, spanning protocol to physical analysis in a single tool. The new Tektronix TLA7SA16 and TLA7SA08 Logic Protocol Analyzer modules, bus support software, and probes combine to give PCIe 3.0 developers an exclusive time-correlated view of system behavior, starting with protocol analysis and working down to the physical layer to debug the root cause of elusive problems.

The Tektronix PCIe 3.0 test solution builds on Tektronix’ previous generation PCIe protocol and logic analysis offerings broadly adopted across the industry by silicon vendors, system designers and high-performance embedded engineers. It also expands on previously announced offerings for PCIe 3.0 electrical test and validation including Serial Data Link Analysis (SDLA) Software for the DPO/DSA/MSO70000 Series oscilloscopes.

The Tektronix Logic Protocol Analyzer delivers the best of both a protocol analyzer and a logic analyzer for PCIe design, test and debug. Protocol analyzer capabilities include flexible, integrated data views for analyzing and displaying protocol traffic flow correlated with physical layer events. Logic analyzer capabilities include a wide range of probing options, sophisticated triggering and time-correlated waveform and disassembled listing data displays of raw symbols and lane data. The new PCIe solution expands the TLA7000 Series high-performance logic analyzer family and works with TLA7000 mainframes including TLA7012 portable and TLA7016 benchtop models.

“As PCI Express bus speeds and complexity increase, it’s important that the protocol and physical layer testing tools keep pace,” said Jim Pappas, director of initiative marketing for Intel Corporation. “With its Logic Protocol Analyzer, Tektronix is among those companies expanding the approach to protocol analysis with a logic analyzer that can help continue timely delivery of PCIe 3.0 silicon and systems to consumers.”

Integrated Views of Protocol Behavior, Physical Activity

Using real-time and HW-accelerated, post-processed statistics displayed in the new Summary Profile Window, the Logic Protocol Analyzer lets users quickly assess system health, identifying artifacts and patterns of interest (errors, specific transaction types, ordered sets, etc.). A single innovative Transaction Window provides views of protocol behavior at the packet and transaction level interspersed with physical layer activity, while the unique Listing Window shows packet details at the symbol level by lane. Further, individual lane activity can be correlated with analog waveforms from a high bandwidth oscilloscope in the Waveform Window.

The new TLA7SA16 and TLA7SA08 Logic Protocol Analyzer modules provide x8 and x4 lane support respectively with support for 8.0 GTs acquisition rates and support for PCI Express link widths from x1 through x16. The modules are fully compatible with previous generation PCI Express specifications. The modules dynamically track changes in link width, link speed, bus power state changes and include a powerful trigger state machine that spans all layers of the protocol (physical, data, link and transaction).

Up to 16 GB deep memory (for x16 link) increases chances of capturing both an error and the fault that caused that error. To make maximum use of memory, users can store everything on the bus or use powerful, real-time hardware filtering and conditional storage to store selected transactions over an 11 day period.

The Tektronix PCIe 3.0 solution delivers a comprehensive selection of probes, ensuring that test equipment doesn’t impose design constraints. Probing solutions, including midbus, slot interposer and solder-down connectors, support PCIe3 channel lengths up to 24” with 2 connectors, offering minimal electrical loading with the highest signal fidelity and active equalization to ensure accurate data recovery of closed eyes. All probes feature a graphical lane swizzling capability for maximum flexibility to accommodate unique circuit board layouts.

“As bus speeds and complexity increase from one generation to the next, engineers face increasingly more difficult challenges to quickly identify the cause of elusive hardware and software problems that threaten their product development schedules,” said Dave Farrell, managing director of the Logic Analyzer Product Line, Tektronix. “For PCIe 3.0, we are changing the rules for protocol and logic analysis. The resulting solution is greater than the sum of the parts and will dramatically boost PCIe engineering productivity.”

PCIe 3.0 Electrical Validation and Debug

In addition to the new Logic Protocol Analyzer solution, Tektronix provides a full set of test equipment for PCIe 3.0 electrical validation and debug. At 20 GHz, the DPO/DSA/MSO70000 Series oscilloscope enables capture of the 5th harmonic of the 4 GHz fundamental. Serial Data Link Analysis software enables channel de-convolution and de-emphasis removal. DPOJET Jitter and Eye-diagram Analysis software provides jitter, eye-diagram and parametric testing. And the P7520 TriMode™ Differential Probe is available for validation and debug of chip-to-chip links, including common mode measurements.

Find out more at www.tektronix.com

Company profile:  Tektronix